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Verilog程序如下,则下列说法中正确的是()。moduleLearn4_2(A,EN,Y)output[7:0]Y;input[2:0]A;inputEN;reg[7:0]Y;wire[3:0]temp={A,EN};alwayscase(temp)4’b0001:Y=8’b00000001;4’b0011:Y=8’b00000010;4’b0101:Y=8’b00000100;4’b0111:Y=8’b00001000;4’b1001:Y=8’b00010000;4’b1011:Y=8’b00100000;4’b1101:Y=8’b01000000;4’b1111:Y=8’b10000000;default:Y=8’b1111111;endcaseendmodule
A.当EN=1时,将二进制数A转换为其对应的独热码
B.因为缺少break,程序功能将无法实现
C.当EN=0时将输出全部置为1
D.该程序会生成锁存器
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